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Systems engineering for FPGA design in the age of AI
Field-programmable gate array (FPGA) teams meet artificial intelligence (AI) twice: as a tool that drafts register-transfer-level (RTL) code and testbenches, and as a component — a quantized inference core instantiated in fabric beside deterministic logic. The association’s AI-Augmented Systems Engineering course treats both. This post makes a stronger claim: FPGA engineering is not just another audience for that material. It is the discipline where the material’s central problems become concrete first, and where several of them already have working answers.
Published 2026-07-05.
FPGA teams meet the shift first
Hardware projects have long been verification-dominated; writing the RTL was never the schedule risk. AI-drafted RTL pushes generation cost toward zero and leaves that structure intact, which makes hardware’s cost profile the general case across engineering. Software teams are now discovering that specification and verification are the product; FPGA teams have operated on that assumption since constrained-random verification displaced directed tests. The transition the course describes — implementors pushed up into the systems engineer’s role — is not a forecast for FPGA engineers. It is a description of the existing job, minus the discipline’s name.
Coverage closure rehearses statistical assurance
Hardware verification never accepted “the tests pass” as evidence. It asks what fraction of the stimulus space was exercised, against which assertions, and what remains uncovered. That is the epistemic posture a learned component demands, because a neural network offers no other kind of guarantee: no proof over the input space, only measured behavior over a sampled one. Functional coverage closure and statistical validation of a learned component are the same move — define the operating space, sample it deliberately, measure, and state the residual. FPGA verification engineers already hold the expertise the machine-learning field is reinventing under other names.
A frozen network splits verification in two
An inference core in fabric divides assurance into two layers, and the boundary is the frozen, quantized network. Below the boundary: does the RTL implement the quantized model bit-exactly? That is a classical equivalence problem — deterministic and checkable with standard hardware methods, because fixed-point fabric inference is cycle-accurate and bit-reproducible in a way floating-point inference on a graphics processor is not. Above the boundary: does the model meet the system requirement over its operating distribution? That question is statistical, and no amount of implementation-level verification closes it. Much of the anxiety about “verifying AI” comes from blurring these layers. On an FPGA nothing forces the blur: the implementation claim closes completely, and the residual risk sits exactly where it belongs — in the model and its training data. Locating risk precisely is most of what a safety case is.
Weights are hardware
Once the weights ship inside the bitstream, a model update is a hardware change. It enters the same change control as an RTL edit: re-synthesis, regression, timing closure, sign-off. That discipline is stricter than mainstream machine-learning operations practice, and it pulls the training pipeline in with it. The dataset version, the training script, and the quantization recipe become configuration items, because they determine bits in the shipped artifact as surely as source code does. The consequence for specification: a learned core’s datasheet must state its training distribution the way any part’s datasheet states operating conditions, and an input from outside that distribution is out-of-spec operation, not surprising behavior.
The wrapper carries the safety case
Function allocation — the central act in the course — is physical on an FPGA: fabric is partitioned between a learned core and the deterministic logic around it. The strongest architectural consequence is to allocate the safety case to the wrapper, not the network. Deterministic monitor logic bounds the core’s outputs, checks inputs against the specified training envelope, and switches to a verified fallback within a bounded number of cycles. Runtime-assurance architectures of this shape are established in the safety literature; the FPGA is their natural substrate, because the monitor is independent parallel hardware that shares the core’s clock without sharing its failure modes — not software layered on the stack it polices. Certification then rests on exhaustively verifiable logic, and the learned core needs to be only as trustworthy as the envelope the wrapper enforces.
What the course covers
The course is organized around two dualities — AI as a tool for doing systems engineering, and AI as a component that must itself be engineered — and runs as 15 weekly lecture decks in three parts, all free Microsoft PowerPoint (.pptx) downloads. Part 1, Foundations (weeks 1–7): lifecycle models, requirements and concept of operations, function allocation, Model-Based Systems Engineering (MBSE), trade studies, and graph-theoretic system analysis. Part 2, Assurance (weeks 8–12): verification and validation of learned components, reliability and resilience, risk, cost and schedule management, and certification. Part 3, Synthesis (weeks 13–15): human-systems integration, integration strategy and agentic workflows, and capstone presentations.
The closing lens is a complementarity framework — AI as accelerator, explorer, and pattern recognizer, each leaving a distinct human responsibility — and it maps directly onto FPGA practice: drafted RTL the engineer judges, implementation spaces the engineer bounds and selects from, and an in-fabric detector whose failure modes the engineer owns. Allocate by mode, verify by evidence, certify by accountability.
Where to start
Start with the overview deck, then Part 1. The full lecture list is on the course page; the mapping onto a standard graduate systems-engineering curriculum is at where the course fits.