Resources

Vendor-neutral references for working FPGA engineers. All free to read. Most link directly to the original source.

Career

Salary survey results
Annual compensation survey for FPGA engineers, broken down by region, experience, and specialization. Survey publication pending.
Interview preparation
Question patterns, take-home formats, and what to ask in return. Draft in review.
Career roadmap
Pathway from entry-level RTL through senior verification or design leadership, with the skills and projects that mark each transition. Draft in review.
Skills gap self-assessment
A short questionnaire to identify which areas — verification, timing closure, vendor flow, RTL fundamentals — would most improve your effectiveness in the next year. Draft in review.

Technical references

Numeric formats in the Altera FPGA AI Suite IP
The four arch_precision block-floating-point formats (FP11, FP12AGX, FP13AGX, FP16) at the bit level, a worked quantization example, where the pipeline uses fp32 and fp16 instead, multiplications per DSP block by device family, and the rest of the global parameter group. Based on the 2025.1 reference manual, with every number traced to it.

Tooling

CovertEDA
Open-source replacement GUI for the major vendor toolchains. Built in Rust and Tauri. GUIs are reaching end of life — coding agents (Claude Code, opencode, Codex) with 2026 models drive the same vendor tooling headless. See the tools page for details.

Community

Mailing list
Low-volume announcements only. To subscribe, email contact@fpgapa.org.
GitHub organization
github.com/fpga-professional-association
Volunteer opportunities
See the contribute page for working groups, content contributions, and chapter formation.